1. Field of the Invention
The present invention relates to a method for controlling for refreshing of data in a dynamic random access memory unit, for example, in random access memory (RAM) large-scale memory units of a central control unit of an electronic switching system. In such memory units, the central control unit has relatively many, long connections with high running times between its many components. In such a system, there is a plurality of groups of memory cells, whereby refreshing is executed in stages. In particular, refreshing of the memory is performed in groups, so that normal memory cycles, i.e., read and/or write cycles, can be executed between the successively following two groups. A refresh generator is provided for generating refresh voltages respectively required for the refreshing operation and at least a single timer is provided for measuring intervals. A short pause of, for example, 400 ns, is provided between the end of the memory cycle or write cycle, on the one hand, and a next possible such memory cycle following immediately thereafter in close proximity, on the other hand. Such a system can contain one or more RAM semiconductor chips. For a RAM memory unit containing a maximum of 128 groups of memory cells to be successively refreshed in and of themselves, 128 refresh cycles within a maximum duration of, for example, 2 ms is required for refreshing all groups therein. More specifically, in such a method, the present invention is concerned with avoiding time losses caused by the known refresh cycle control.
2. Description of the Prior Art
Each memory cell in such a RAM memory unit must be refreshed by way of the refresh cycles controlled by a refresh generator in regular intervals, for example, after a maximum duration of 2 ms. Otherwise, the memory cells would lose their stored information relatively quickly due to self-discharge. In the prior art, as well as in the present invention, a single refresh generator can thereby basically supply not only a single RAM memory unit, but can even supply a great number of different RAM memory units with their individually-required refresh cycles.
Frequently, an entire RAM memory unit that is in need of refreshing is not simultaneously refreshed. On the contrary, the refreshing is carried out in stages, in a respectively small group of memory cells of the RAM memory unit. For example, in a RAM memory unit constructed matrix-like and having, for example, 128 groups, only all memory cells of a single memory row or of a single memory column are respectively refreshed. Read and write cycles, i.e., normal memory cycles, can be executed between the stages. Refreshing the entire memory unit then occurs successively in many individual refresh cycles, each of which lasts far less than 1 .mu.s, with respectively long-lasting (for example, 15 .mu.s) interruptions between the refresh cycles that can be used for subsequent memory cycles. In this case, in particular, the time interval between two refresh cycles amounts to, for example, that maximum duration of 2 ms, for example, divided by the number of groups of memory cells of the RAM memory unit, i.e., given a RAM memory unit having 128 groups, for example, EQU 2 ms.div.128=about 15 .mu.s.
The known RAM memory units are refreshed, for example, in that they use a request signal to request a refresh cycle from a central computing unit and, finally, are granted the refresh cycle by way of a grant signal.
As in the prior art, a refresh cycle (5 in FIG. 2) does not occur between all memory cycles (1/2/3/4) in the present invention. A refreshing of all memory cells in each memory cycle is generally neither necessary nor economical. Every refresh cycle, in particular, generates a relatively high load on the power supply of the RAM memory unit. At least a longer time interval in therefore placed between two refresh cycles triggered by memory cycles, many memory cycles (1/2/3/4) being in fact capable of taking place during this longer time interval but no refresh cycles.
In the known RAM memory units, no access from the exterior, i.e., from an externally-connected processor, to the appertaining RAM memory unit is permitted during the duration of a refresh cycle, i.e., no normal memory cycle is executed, such as a read cycle or a write cycle. Normally, therefore, the RAM memory unit is inhibited for the initiation of such normal memory cycles during the refresh cycle. Only when the refresh cycle for refreshing the appertaining memory cells has been carried out is the RAM memory unit enable again for external accesses, i.e., for the next read and/or write cycles.